M31 and Ambiq Optimize TSMC N12e Power Efficiency for Edge AI

The collaboration integrates an optimized SPSRAM memory compiler with an ultra-low-leakage standard-cell library to address the demands of always-on edge applications. By utilizing Ambiq’s cascade-style methodology alongside M31’s circuit innovations, the platform achieves a 50% reduction in leakage power. This technical synergy allows developers to hit aggressive performance, power, and area targets without sacrificing compute responsiveness.

The memory compiler features a dual-rail architecture capable of reaching 500 MHz at near-threshold voltages while keeping retention leakage minimal. According to Jayanta Lahiri, VP at M31, this co-optimized approach provides a practical path for designers to meet the complex requirements of next-generation edge intelligence. Scott Hanson, CTO and Founder of Ambiq, emphasized that building energy efficiency into the foundation of a system-on-chip is critical as edge devices take on increasingly sophisticated AI workloads.